Principal Analog/Mixed Signal Engineer

About the Role

This is a principal-level engineering role on a small, high-output chip design team building a novel thermodynamic computing architecture that uses thermal noise in CMOS to perform probabilistic sampling. The team has already completed multiple tape-outs and is now defining the architecture for three upcoming chips. You will own significant portions of chip design and have the opportunity to serve as design lead on one of those chips.

What You'll Do

• Lead the design of analog and mixed-signal blocks including ADCs, PLLs, bandgaps, regulators, high-speed SerDes, oscillators, and dividers for upcoming tape-outs.

• Own large sections of chip architecture and potentially serve as design lead for one of three planned chips.

• Perform hands-on layout work and design verification including DRC, ERC, and LVS.

• Collaborate with IC, systems, physics, and algorithms teams to translate probabilistic computing concepts into silicon implementations.

• Contribute to lab testing and validation of fabricated chips using signal generators, spectrum analyzers, and oscilloscopes.

What We're Looking For

• 6 or more years of experience in CMOS analog and mixed-signal circuit design.

• Proven experience designing mixed-signal blocks such as PLLs, SerDes, ADCs, or oscillators.

• Multiple completed tape-outs, ideally in FinFET or 28nm/65nm process nodes.

• MS or PhD in Electrical Engineering with a focus on circuits or IC design.

• Proficiency with Cadence simulation including PEX, Monte Carlo, and corners analysis.

• Hands-on layout experience beyond design review.

• Familiarity with Python or C is a plus.

• Background from national labs, semiconductor, or research-driven hardware organizations is a strong fit.

Compensation & Benefits

Base salary range: $200,000 to $325,000 USD annually, plus equity. Visa sponsorship is available.

Location

On-site in Boston, Massachusetts, United States. Candidates must be based in or willing to relocate to Boston.