ASIC Physical Design Engineer - Library Characterization

ASIC Physical Design Engineer - Library Characterization

Contract - 9 Months

Cork - Remote

My client, a leading technology organisation is on the lookout for an ASIC Physical Design Engineer to join their team on an initial 9 month contract with view for extension.

The Job:

• Perform characterization of timing, power, pin capacitance and Liberty models for analogue and GPIO libraries.
• Carry out library characterization and timing-related activities, including LVF, AOCV, POCV and SOCV.
• Correlate results between different timing sign-off tools and SPICE simulations across timing, noise and Monte Carlo metrics.
• Work on standard-cell library characterization and support the development and validation of characterization flows.
• Perform ASIC physical design activities, including synthesis, floorplanning, power planning, placement, CTS and routing.
• Support static timing analysis (STA) and timing sign-off activities.
• Work with SPICE extraction, modelling and ageing/reliability models for advanced technology nodes.
• Develop and automate new flows and methodologies to improve overall team productivity.
• Use scripting and automation to support engineering workflows and improve characterization and physical design processes.
• Contribute to the development and validation of new methodologies, working closely with engineering teams to improve existing processes.

Have you:

• 3+ years of experience in ASIC physical design, library characterization, timing or a closely related semiconductor engineering discipline.
• Experience with characterization of timing, power and pin capacitance for analogue and/or GPIO libraries.
• Functional understanding of GPIO and analogue IPs and hands-on experience with standard-cell library characterization.
• Experience with characterization tools and simulators such as Silicon Smart, HSPICE, PrimeSim, AFS and Spectre, with knowledge of Liberty format.
• Strong knowledge of ASIC physical design, including synthesis, floorplanning, power planning, placement, CTS, routing and STA.
• Experience with tools such as Design Compiler, IC Compiler II (ICC2), Fusion Compiler, PrimeTime, StarRC and Innovus.
• Extensive experience with timing libraries, LVF, AOCV, POCV and/or SOCV, including timing sign-off activities.
• Strong understanding of SPICE extraction, modelling and ageing/reliability models for advanced technology nodes.
• Strong Python programming and scripting skills, with Perl, TCL and Bash considered advantageous.
• Strong problem-solving, communication and teamwork skills, with a self-motivated approach and willingness to learn and develop new methodologies.

Berkley Business & Technology is a specialist consultancy, recruiting professionals for organizations throughout Ireland, UK & Europe; for more information go to www.berkley-group.com.

If you would like to discuss this vacancy further or to discuss your career options in confidence, please send your profile to owanszaft@berkley-group.com